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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit9d4a1bf2ba936499277b96054fbc83c478c0c6be (patch)
treed4ced7dbf19e8c0e044bec654f3ea1c82cd809cf /src/arch/arm/insts
parent28023f6f3d752fe600e4f610549ae27541b2ebce (diff)
downloadgem5-9d4a1bf2ba936499277b96054fbc83c478c0c6be.tar.xz
ARM: Explicitly keep track of the second destination for double loads/stores.
Diffstat (limited to 'src/arch/arm/insts')
-rw-r--r--src/arch/arm/insts/mem.cc2
-rw-r--r--src/arch/arm/insts/mem.hh97
2 files changed, 98 insertions, 1 deletions
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 6cbe08ac8..521499847 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -66,7 +66,7 @@ void
Memory::printInst(std::ostream &os, AddrMode addrMode) const
{
printMnemonic(os);
- printReg(os, dest);
+ printDest(os);
os << ", [";
printReg(os, base);
if (addrMode != AddrMd_PostIndex) {
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index 6ed99ba5b..dc4b7d627 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -88,6 +88,12 @@ class Memory : public PredOp
printOffset(std::ostream &os) const
{}
+ virtual void
+ printDest(std::ostream &os) const
+ {
+ printReg(os, dest);
+ }
+
void printInst(std::ostream &os, AddrMode addrMode) const;
};
@@ -112,6 +118,28 @@ class MemoryImm : public Memory
}
};
+// The address is a base register plus an immediate.
+class MemoryDImm : public MemoryImm
+{
+ protected:
+ IntRegIndex dest2;
+
+ MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add, int32_t _imm)
+ : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
+ dest2(_dest2)
+ {}
+
+ void
+ printDest(std::ostream &os) const
+ {
+ MemoryImm::printDest(os);
+ os << ", ";
+ printReg(os, dest2);
+ }
+};
+
// The address is a shifted register plus an immediate
class MemoryReg : public Memory
{
@@ -165,6 +193,30 @@ class MemoryReg : public Memory
}
};
+class MemoryDReg : public MemoryReg
+{
+ protected:
+ IntRegIndex dest2;
+
+ MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add,
+ int32_t _shiftAmt, ArmShiftType _shiftType,
+ IntRegIndex _index)
+ : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add,
+ _shiftAmt, _shiftType, _index),
+ dest2(_dest2)
+ {}
+
+ void
+ printDest(std::ostream &os) const
+ {
+ MemoryReg::printDest(os);
+ os << ", ";
+ printReg(os, dest2);
+ }
+};
+
template<class Base>
class MemoryOffset : public Base
{
@@ -183,6 +235,21 @@ class MemoryOffset : public Base
_shiftAmt, _shiftType, _index)
{}
+ MemoryOffset(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add, int32_t _imm)
+ : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
+ {}
+
+ MemoryOffset(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add,
+ int32_t _shiftAmt, ArmShiftType _shiftType,
+ IntRegIndex _index)
+ : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
+ _shiftAmt, _shiftType, _index)
+ {}
+
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
@@ -210,6 +277,21 @@ class MemoryPreIndex : public Base
_shiftAmt, _shiftType, _index)
{}
+ MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add, int32_t _imm)
+ : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
+ {}
+
+ MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add,
+ int32_t _shiftAmt, ArmShiftType _shiftType,
+ IntRegIndex _index)
+ : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
+ _shiftAmt, _shiftType, _index)
+ {}
+
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
@@ -237,6 +319,21 @@ class MemoryPostIndex : public Base
_shiftAmt, _shiftType, _index)
{}
+ MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add, int32_t _imm)
+ : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
+ {}
+
+ MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
+ IntRegIndex _base, bool _add,
+ int32_t _shiftAmt, ArmShiftType _shiftType,
+ IntRegIndex _index)
+ : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
+ _shiftAmt, _shiftType, _index)
+ {}
+
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{