ARM: Add a base class for the RFE instruction.

2 files changed, 49 insertions, 0 deletions

diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 521499847..394c159d1 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -62,6 +62,31 @@ Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+string
+RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    switch (mode) {
+      case DecrementAfter:
+        printMnemonic(ss, "da");
+        break;
+      case DecrementBefore:
+        printMnemonic(ss, "db");
+        break;
+      case IncrementAfter:
+        printMnemonic(ss, "ia");
+        break;
+      case IncrementBefore:
+        printMnemonic(ss, "ib");
+        break;
+    }
+    printReg(ss, base);
+    if (wb) {
+        ss << "!";
+    }
+    return ss.str();
+}
+
 void
 Memory::printInst(std::ostream &os, AddrMode addrMode) const
 {
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index dc4b7d627..d5b5d3519 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -63,6 +63,30 @@ class Swap : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+// The address is a base register plus an immediate.
+class RfeOp : public PredOp
+{
+  public:
+    enum AddrMode {
+        DecrementAfter,
+        DecrementBefore,
+        IncrementAfter,
+        IncrementBefore
+    };
+  protected:
+    IntRegIndex base;
+    AddrMode mode;
+    bool wb;
+
+    RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+          IntRegIndex _base, AddrMode _mode, bool _wb)
+        : PredOp(mnem, _machInst, __opClass),
+          base(_base), mode(_mode), wb(_wb)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class Memory : public PredOp
 {
   public: