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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-15 13:30:46 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 14:23:19 +0000 |
| commit | e97a1fe390a91f30042d683ebc5e654d39844eda (patch) | |
| tree | cb65b1a95de5bec2642af955ad54205f159f9db0 /src/arch/arm/interrupts.cc | |
| parent | 4ccb1ea710dcdcf179726448596b96c8e44f743a (diff) | |
| download | gem5-e97a1fe390a91f30042d683ebc5e654d39844eda.tar.xz | |
arch-arm: Replace direct use cpsr.el with currEL helper
The patch is replacing it in places where the current EL could be using
AArch32, hence leading to an incorrect ExceptionLevel.
Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/interrupts.cc')
| -rw-r--r-- | src/arch/arm/interrupts.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc index 3d841e9f8..e2febb35e 100644 --- a/src/arch/arm/interrupts.cc +++ b/src/arch/arm/interrupts.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009, 2012-2013, 2016 ARM Limited + * Copyright (c) 2009, 2012-2013, 2016, 2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -58,7 +58,7 @@ ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const SCR scr; HCR hcr; hcr = tc->readMiscReg(MISCREG_HCR); - ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el); + ExceptionLevel el = currEL(tc); bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit; if (!highest_el_is_64) |