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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
| commit | 48525f581c6233b8f7a8a872c5774d4e245f431c (patch) | |
| tree | d6bfb77abb6e70684f04d21b47731ed7a02bcf94 /src/arch/arm/intregs.hh | |
| parent | d188821d3700ee42e01fc43c9ef17568991fb3ff (diff) | |
| download | gem5-48525f581c6233b8f7a8a872c5774d4e245f431c.tar.xz | |
ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
Diffstat (limited to 'src/arch/arm/intregs.hh')
| -rw-r--r-- | src/arch/arm/intregs.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh index 78ad39ee2..b5f955c4b 100644 --- a/src/arch/arm/intregs.hh +++ b/src/arch/arm/intregs.hh @@ -104,6 +104,7 @@ enum IntRegIndex INTREG_UREG0, INTREG_RHI, INTREG_RLO, + INTREG_CONDCODES, NUM_INTREGS, NUM_ARCH_INTREGS = INTREG_PC + 1, |