arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli    (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt       (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole           (AArch64 NEON, validation)
Ali Saidi            (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang         (AArch64 Linux support)
Rene De Jong         (AArch64 Linux support, performance opt.)
Matt Horsnell        (AArch64 MP, validation)
Matt Evans           (device models, code integration, validation)
Chris Adeniyi-Jones  (AArch64 syscall-emulation)
Prakash Ramrakhyani  (validation)
Dam Sunwoo           (validation)
Chander Sudanthi     (validation)
Stephan Diestelhorst (validation)
Andreas Hansson      (code integration, performance opt.)
Eric Van Hensbergen  (performance opt.)
Gabe Black

1 files changed, 177 insertions, 11 deletions

diff --git a/src/arch/arm/intregs.hh b/src/arch/arm/intregs.hh
index 3fe00b765..fa18aa68d 100644
--- a/src/arch/arm/intregs.hh
+++ b/src/arch/arm/intregs.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2013 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -83,6 +83,9 @@ enum IntRegIndex
     INTREG_R14_MON,
     INTREG_LR_MON = INTREG_R14_MON,
 
+    INTREG_R13_HYP,
+    INTREG_SP_HYP = INTREG_R13_HYP,
+
     INTREG_R13_ABT,
     INTREG_SP_ABT = INTREG_R13_ABT,
     INTREG_R14_ABT,
@@ -108,7 +111,7 @@ enum IntRegIndex
     INTREG_R14_FIQ,
     INTREG_LR_FIQ = INTREG_R14_FIQ,
 
-    INTREG_ZERO, // Dummy zero reg since there has to be one.
+    INTREG_ZERO,
     INTREG_UREG0,
     INTREG_UREG1,
     INTREG_UREG2,
@@ -117,12 +120,54 @@ enum IntRegIndex
     INTREG_CONDCODES_V,
     INTREG_CONDCODES_GE,
     INTREG_FPCONDCODES,
+    INTREG_DUMMY, // Dummy reg used to throw away int reg results
+
+    INTREG_SP0,
+    INTREG_SP1,
+    INTREG_SP2,
+    INTREG_SP3,
 
     NUM_INTREGS,
-    NUM_ARCH_INTREGS = INTREG_PC + 1,
+    NUM_ARCH_INTREGS = 32,
+
+    /* AArch64 registers */
+    INTREG_X0 = 0,
+    INTREG_X1,
+    INTREG_X2,
+    INTREG_X3,
+    INTREG_X4,
+    INTREG_X5,
+    INTREG_X6,
+    INTREG_X7,
+    INTREG_X8,
+    INTREG_X9,
+    INTREG_X10,
+    INTREG_X11,
+    INTREG_X12,
+    INTREG_X13,
+    INTREG_X14,
+    INTREG_X15,
+    INTREG_X16,
+    INTREG_X17,
+    INTREG_X18,
+    INTREG_X19,
+    INTREG_X20,
+    INTREG_X21,
+    INTREG_X22,
+    INTREG_X23,
+    INTREG_X24,
+    INTREG_X25,
+    INTREG_X26,
+    INTREG_X27,
+    INTREG_X28,
+    INTREG_X29,
+    INTREG_X30,
+    INTREG_X31,
+
+    INTREG_SPX = NUM_INTREGS,
 
     /* All the aliased indexes. */
-    
+
     /* USR mode */
     INTREG_R0_USR = INTREG_R0,
     INTREG_R1_USR = INTREG_R1,
@@ -195,6 +240,25 @@ enum IntRegIndex
     INTREG_PC_ABT = INTREG_PC,
     INTREG_R15_ABT = INTREG_R15,
 
+    /* HYP mode */
+    INTREG_R0_HYP = INTREG_R0,
+    INTREG_R1_HYP = INTREG_R1,
+    INTREG_R2_HYP = INTREG_R2,
+    INTREG_R3_HYP = INTREG_R3,
+    INTREG_R4_HYP = INTREG_R4,
+    INTREG_R5_HYP = INTREG_R5,
+    INTREG_R6_HYP = INTREG_R6,
+    INTREG_R7_HYP = INTREG_R7,
+    INTREG_R8_HYP = INTREG_R8,
+    INTREG_R9_HYP = INTREG_R9,
+    INTREG_R10_HYP = INTREG_R10,
+    INTREG_R11_HYP = INTREG_R11,
+    INTREG_R12_HYP = INTREG_R12,
+    INTREG_LR_HYP = INTREG_LR,
+    INTREG_R14_HYP = INTREG_R14,
+    INTREG_PC_HYP = INTREG_PC,
+    INTREG_R15_HYP = INTREG_R15,
+
     /* UND mode */
     INTREG_R0_UND = INTREG_R0,
     INTREG_R1_UND = INTREG_R1,
@@ -244,11 +308,26 @@ enum IntRegIndex
 
 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
 
+const IntRegMap IntReg64Map = {
+    INTREG_R0,      INTREG_R1,      INTREG_R2,      INTREG_R3,
+    INTREG_R4,      INTREG_R5,      INTREG_R6,      INTREG_R7,
+    INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
+    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
+    INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
+    INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
+    INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
+    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
+};
+
 const IntRegMap IntRegUsrMap = {
     INTREG_R0_USR,  INTREG_R1_USR,  INTREG_R2_USR,  INTREG_R3_USR,
     INTREG_R4_USR,  INTREG_R5_USR,  INTREG_R6_USR,  INTREG_R7_USR,
     INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
-    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
+    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -258,11 +337,33 @@ INTREG_USR(unsigned index)
     return IntRegUsrMap[index];
 }
 
+const IntRegMap IntRegHypMap = {
+    INTREG_R0_HYP,  INTREG_R1_HYP,  INTREG_R2_HYP,  INTREG_R3_HYP,
+    INTREG_R4_HYP,  INTREG_R5_HYP,  INTREG_R6_HYP,  INTREG_R7_HYP,
+    INTREG_R8_HYP,  INTREG_R9_HYP,  INTREG_R10_HYP, INTREG_R11_HYP,
+    INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
+};
+
+static inline IntRegIndex
+INTREG_HYP(unsigned index)
+{
+    assert(index < NUM_ARCH_INTREGS);
+    return IntRegHypMap[index];
+}
+
 const IntRegMap IntRegSvcMap = {
     INTREG_R0_SVC,  INTREG_R1_SVC,  INTREG_R2_SVC,  INTREG_R3_SVC,
     INTREG_R4_SVC,  INTREG_R5_SVC,  INTREG_R6_SVC,  INTREG_R7_SVC,
     INTREG_R8_SVC,  INTREG_R9_SVC,  INTREG_R10_SVC, INTREG_R11_SVC,
-    INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
+    INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -276,7 +377,11 @@ const IntRegMap IntRegMonMap = {
     INTREG_R0_MON,  INTREG_R1_MON,  INTREG_R2_MON,  INTREG_R3_MON,
     INTREG_R4_MON,  INTREG_R5_MON,  INTREG_R6_MON,  INTREG_R7_MON,
     INTREG_R8_MON,  INTREG_R9_MON,  INTREG_R10_MON, INTREG_R11_MON,
-    INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
+    INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -290,7 +395,11 @@ const IntRegMap IntRegAbtMap = {
     INTREG_R0_ABT,  INTREG_R1_ABT,  INTREG_R2_ABT,  INTREG_R3_ABT,
     INTREG_R4_ABT,  INTREG_R5_ABT,  INTREG_R6_ABT,  INTREG_R7_ABT,
     INTREG_R8_ABT,  INTREG_R9_ABT,  INTREG_R10_ABT, INTREG_R11_ABT,
-    INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
+    INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -304,7 +413,11 @@ const IntRegMap IntRegUndMap = {
     INTREG_R0_UND,  INTREG_R1_UND,  INTREG_R2_UND,  INTREG_R3_UND,
     INTREG_R4_UND,  INTREG_R5_UND,  INTREG_R6_UND,  INTREG_R7_UND,
     INTREG_R8_UND,  INTREG_R9_UND,  INTREG_R10_UND, INTREG_R11_UND,
-    INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
+    INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -318,7 +431,11 @@ const IntRegMap IntRegIrqMap = {
     INTREG_R0_IRQ,  INTREG_R1_IRQ,  INTREG_R2_IRQ,  INTREG_R3_IRQ,
     INTREG_R4_IRQ,  INTREG_R5_IRQ,  INTREG_R6_IRQ,  INTREG_R7_IRQ,
     INTREG_R8_IRQ,  INTREG_R9_IRQ,  INTREG_R10_IRQ, INTREG_R11_IRQ,
-    INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
+    INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -332,7 +449,11 @@ const IntRegMap IntRegFiqMap = {
     INTREG_R0_FIQ,  INTREG_R1_FIQ,  INTREG_R2_FIQ,  INTREG_R3_FIQ,
     INTREG_R4_FIQ,  INTREG_R5_FIQ,  INTREG_R6_FIQ,  INTREG_R7_FIQ,
     INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
-    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
+    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
+    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 };
 
 static inline IntRegIndex
@@ -351,6 +472,51 @@ intRegInMode(OperatingMode mode, int reg)
     return mode * intRegsPerMode + reg;
 }
 
+static inline int
+flattenIntRegModeIndex(int reg)
+{
+    int mode = reg / intRegsPerMode;
+    reg = reg % intRegsPerMode;
+    switch (mode) {
+      case MODE_USER:
+      case MODE_SYSTEM:
+        return INTREG_USR(reg);
+      case MODE_FIQ:
+        return INTREG_FIQ(reg);
+      case MODE_IRQ:
+        return INTREG_IRQ(reg);
+      case MODE_SVC:
+        return INTREG_SVC(reg);
+      case MODE_MON:
+        return INTREG_MON(reg);
+      case MODE_ABORT:
+        return INTREG_ABT(reg);
+      case MODE_HYP:
+        return INTREG_HYP(reg);
+      case MODE_UNDEFINED:
+        return INTREG_UND(reg);
+      default:
+        panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
+                curTick(), reg, mode);
+    }
+}
+
+
+static inline IntRegIndex
+makeSP(IntRegIndex reg)
+{
+    if (reg == INTREG_X31)
+        reg = INTREG_SPX;
+    return reg;
+}
+
+
+static inline bool
+isSP(IntRegIndex reg)
+{
+    return reg == INTREG_SPX;
+}
+
 }
 
 #endif