arm: Panics in miscreg read functions can be tripped by O3 model

Unimplemented miscregs for the generic timer were guarded by panics
in arm/isa.cc which can be tripped by the O3 model if it speculatively
executes a wrong path containing a mrs instruction with a bad miscreg
index. These registers were flagged as implemented and accessible.
This patch changes the miscreg info bit vector to flag them as
unimplemented and inaccessible. In this case, and UndefinedInst
fault will be generated if the register access is not trapped
by a hypervisor.

1 files changed, 15 insertions, 16 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 4f1ef91ec..5f8378e09 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -729,30 +729,30 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         return getArchTimer(tc, tc->cpuId())->control();
       // PL1 phys. timer, secure
       //   AArch64
-      case MISCREG_CNTPS_CVAL_EL1:
-      case MISCREG_CNTPS_TVAL_EL1:
-      case MISCREG_CNTPS_CTL_EL1:
+      // case MISCREG_CNTPS_CVAL_EL1:
+      // case MISCREG_CNTPS_TVAL_EL1:
+      // case MISCREG_CNTPS_CTL_EL1:
       // PL2 phys. timer, non-secure
       //   AArch32
-      case MISCREG_CNTHCTL:
-      case MISCREG_CNTHP_CVAL:
-      case MISCREG_CNTHP_TVAL:
-      case MISCREG_CNTHP_CTL:
+      // case MISCREG_CNTHCTL:
+      // case MISCREG_CNTHP_CVAL:
+      // case MISCREG_CNTHP_TVAL:
+      // case MISCREG_CNTHP_CTL:
       //   AArch64
-      case MISCREG_CNTHCTL_EL2:
-      case MISCREG_CNTHP_CVAL_EL2:
-      case MISCREG_CNTHP_TVAL_EL2:
-      case MISCREG_CNTHP_CTL_EL2:
+      // case MISCREG_CNTHCTL_EL2:
+      // case MISCREG_CNTHP_CVAL_EL2:
+      // case MISCREG_CNTHP_TVAL_EL2:
+      // case MISCREG_CNTHP_CTL_EL2:
       // Virtual timer
       //   AArch32
-      case MISCREG_CNTV_CVAL:
-      case MISCREG_CNTV_TVAL:
-      case MISCREG_CNTV_CTL:
+      // case MISCREG_CNTV_CVAL:
+      // case MISCREG_CNTV_TVAL:
+      // case MISCREG_CNTV_CTL:
       //   AArch64
       // case MISCREG_CNTV_CVAL_EL2:
       // case MISCREG_CNTV_TVAL_EL2:
       // case MISCREG_CNTV_CTL_EL2:
-        panic("Generic Timer register not implemented\n");
+      default:
         break;
 
     }
@@ -1902,7 +1902,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           // case MISCREG_CNTV_CVAL_EL2:
           // case MISCREG_CNTV_TVAL_EL2:
           // case MISCREG_CNTV_CTL_EL2:
-            panic("Generic Timer register not implemented\n");
             break;
         }
     }