CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.

1 files changed, 21 insertions, 30 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b8a0fe282..a452991aa 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -39,17 +39,13 @@
  */
 
 #include "arch/arm/isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
 #include "debug/Arm.hh"
 #include "debug/MiscRegs.hh"
 #include "sim/faults.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
 
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
 namespace ArmISA
 {
 
@@ -294,11 +290,15 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
         PCState pc = tc->pcState();
         pc.nextThumb(cpsr.t);
         pc.nextJazelle(cpsr.j);
-#if USE_CHECKER
-        tc->pcStateNoRecord(pc);
-#else
-        tc->pcState(pc);
-#endif //USE_CHECKER
+
+        // Follow slightly different semantics if a CheckerCPU object
+        // is connected
+        CheckerCPU *checker = tc->getCheckerCpuPtr();
+        if (checker) {
+            tc->pcStateNoRecord(pc);
+        } else {
+            tc->pcState(pc);
+        }
     } else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
         misc_reg < MISCREG_CP15_END) {
         panic("Unimplemented CP15 register %s wrote with %#x.\n",
@@ -401,14 +401,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                     oc = sys->getThreadContext(x);
                     oc->getDTBPtr()->allCpusCaching();
                     oc->getITBPtr()->allCpusCaching();
-#if USE_CHECKER
-                    CheckerCPU *checker =
-                        dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+                    // If CheckerCPU is connected, need to notify it.
+                    CheckerCPU *checker = oc->getCheckerCpuPtr();
                     if (checker) {
                         checker->getDTBPtr()->allCpusCaching();
                         checker->getITBPtr()->allCpusCaching();
                     }
-#endif
                 }
                 return;
             }
@@ -426,14 +425,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 oc->getITBPtr()->flushAll();
                 oc->getDTBPtr()->flushAll();
-#if USE_CHECKER
-                CheckerCPU *checker =
-                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+                // If CheckerCPU is connected, need to notify it of a flush
+                CheckerCPU *checker = oc->getCheckerCpuPtr();
                 if (checker) {
                     checker->getITBPtr()->flushAll();
                     checker->getDTBPtr()->flushAll();
                 }
-#endif
             }
             return;
           case MISCREG_ITLBIALL:
@@ -452,16 +450,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                         bits(newVal, 7,0));
                 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
                         bits(newVal, 7,0));
-#if USE_CHECKER
-                CheckerCPU *checker =
-                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+                CheckerCPU *checker = oc->getCheckerCpuPtr();
                 if (checker) {
                     checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
                             bits(newVal, 7,0));
                     checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
                             bits(newVal, 7,0));
                 }
-#endif
             }
             return;
           case MISCREG_TLBIASIDIS:
@@ -472,14 +468,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
                 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
-#if USE_CHECKER
-                CheckerCPU *checker =
-                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+                CheckerCPU *checker = oc->getCheckerCpuPtr();
                 if (checker) {
                     checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
                     checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
                 }
-#endif
             }
             return;
           case MISCREG_TLBIMVAAIS:
@@ -490,14 +483,12 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
                 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
-#if USE_CHECKER
-                CheckerCPU *checker =
-                    dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+                CheckerCPU *checker = oc->getCheckerCpuPtr();
                 if (checker) {
                     checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
                     checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
                 }
-#endif
             }
             return;
           case MISCREG_ITLBIMVA: