summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa.cc
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:30 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:30 -0400
commit23b9792681d4cd794b0ad74138160a37b8bdac8f (patch)
treedd849032f615ec6a5ff43a6a2e93393d8f6fd5f7 /src/arch/arm/isa.cc
parent36f29496a019af4483430f17c4a6028b8dcfb2cf (diff)
downloadgem5-23b9792681d4cd794b0ad74138160a37b8bdac8f.tar.xz
arm: Remove unnecessary boot uncachability
With the recent patches addressing how we deal with uncacheable accesses there is no longer need for the work arounds put in place to enforce certain sections of memory to be uncacheable during boot.
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r--src/arch/arm/isa.cc40
1 files changed, 0 insertions, 40 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9e760fbdf..4358c8b2e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1103,10 +1103,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
tc->getITBPtr()->invalidateMiscReg();
tc->getDTBPtr()->invalidateMiscReg();
-
- if (new_sctlr.c)
- updateBootUncacheable(sctlr_idx, tc);
- return;
}
case MISCREG_MIDR:
case MISCREG_ID_PFR0:
@@ -1656,11 +1652,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
tc->getITBPtr()->invalidateMiscReg();
tc->getDTBPtr()->invalidateMiscReg();
- SCTLR new_sctlr = newVal;
setMiscRegNoEffect(misc_reg, newVal);
- if (new_sctlr.c)
- updateBootUncacheable(misc_reg, tc);
- return;
}
case MISCREG_CONTEXTIDR:
case MISCREG_PRRR:
@@ -1909,38 +1901,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
}
void
-ISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc)
-{
- System *sys;
- ThreadContext *oc;
-
- // Check if all CPUs are booted with caches enabled
- // so we can stop enforcing coherency of some kernel
- // structures manually.
- sys = tc->getSystemPtr();
- for (int x = 0; x < sys->numContexts(); x++) {
- oc = sys->getThreadContext(x);
- // @todo: double check this for security
- SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx);
- if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
- return;
- }
-
- for (int x = 0; x < sys->numContexts(); x++) {
- oc = sys->getThreadContext(x);
- oc->getDTBPtr()->allCpusCaching();
- oc->getITBPtr()->allCpusCaching();
-
- // If CheckerCPU is connected, need to notify it.
- CheckerCPU *checker = oc->getCheckerCpuPtr();
- if (checker) {
- checker->getDTBPtr()->allCpusCaching();
- checker->getITBPtr()->allCpusCaching();
- }
- }
-}
-
-void
ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
bool secure_lookup, uint8_t target_el)
{