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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-10-01 16:02:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-10-01 16:02:45 -0500 |
| commit | b331b02669f95adf4744b1e7db50ad4b231fb704 (patch) | |
| tree | 682fc56d99d2efd7fd45651ad6d1ee35560d19f1 /src/arch/arm/isa.cc | |
| parent | aef4a9904e0324b2aba2ddc212768d5b0c72b566 (diff) | |
| download | gem5-b331b02669f95adf4744b1e7db50ad4b231fb704.tar.xz | |
ARM: Clean up use of TBit and JBit.
Rather tha constantly using ULL(1) << PcXBitShift define those directly.
Additionally, add some helper functions to further clean up the code.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 22447184e..d557cecbb 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -173,7 +173,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) cpsr.j = 1; else cpsr.j = 0; - if (pc & (ULL(1) << PcTBitShift)) + if (isThumb(pc)) cpsr.t = 1; else cpsr.t = 0; @@ -241,9 +241,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); Addr npc = tc->readNextPC() & ~PcModeMask; if (cpsr.j) - npc = npc | (ULL(1) << PcJBitShift); + npc = npc | PcJBit; if (cpsr.t) - npc = npc | (ULL(1) << PcTBitShift); + npc = npc | PcTBit; tc->setNextPC(npc); } else if (misc_reg >= MISCREG_CP15_UNIMP_START && |