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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:44 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:44 -0500 |
commit | 38925ff62126e43ea3d44ace39d908ba38dfc1af (patch) | |
tree | 8c0b37285a3751181aa69f470eb09421f6fc8c5d /src/arch/arm/isa.cc | |
parent | a7e0cbeb36394eec3960dc0e2fb15377880e9e98 (diff) | |
download | gem5-38925ff62126e43ea3d44ace39d908ba38dfc1af.tar.xz |
arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the
ARM architecture model uses the magic MISCREG_CPSR_MODE register to
change the register mappings without actually updating the CPU
mode. This hack is no longer needed since the thread context now
provides a flat interface to the register file. This patch replaces
the CPSR_MODE hack with the flat register interface.
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 99acbb4fd..117873450 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -654,13 +654,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tc->getITBPtr()->invalidateMiscReg(); tc->getDTBPtr()->invalidateMiscReg(); break; - case MISCREG_CPSR_MODE: - // This miscreg is used by copy*Regs to set the CPSR mode - // without updating other CPSR variables. It's used to - // make sure the register map is in such a state that we can - // see all of the registers for the copy. - updateRegMap(val); - return; case MISCREG_L2CTLR: warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", miscRegName[misc_reg], uint32_t(val)); |