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author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
commit | 54a919f22587c75be5e7f0b88d5ec13baba600aa (patch) | |
tree | 65b9d338a6968f16296e761ab7ce9a4867514b7e /src/arch/arm/isa.cc | |
parent | 6368edb281f162e4fbb0a91744992a25134135f4 (diff) | |
download | gem5-54a919f22587c75be5e7f0b88d5ec13baba600aa.tar.xz |
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 17 |
1 files changed, 3 insertions, 14 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ac012fc3c..7991dbfb7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -66,17 +66,6 @@ ISA::clear() miscRegs[MISCREG_SCTLR] = sctlr; miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; - - /* - * Technically this should be 0, but we don't support those - * settings. - */ - CPACR cpacr = 0; - // Enable CP 10, 11 - cpacr.cp10 = 0x3; - cpacr.cp11 = 0x3; - miscRegs[MISCREG_CPACR] = cpacr; - /* Start with an event in the mailbox */ miscRegs[MISCREG_SEV_MAILBOX] = 1; @@ -278,9 +267,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) CPACR valCpacr = val; newCpacr.cp10 = valCpacr.cp10; newCpacr.cp11 = valCpacr.cp11; - if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) { - panic("Disabling coprocessors isn't implemented.\n"); - } + //XXX d32dis isn't implemented. The manual says whether or not + //it works is implementation defined. + newCpacr.asedis = valCpacr.asedis; newVal = newCpacr; } break; |