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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
commit | a679cd917ac4775979e23594de52f1bca407c08c (patch) | |
tree | d48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/arch/arm/isa.cc | |
parent | ac650199eeb62bf05fec11a4f2d7666cbd31331c (diff) | |
download | gem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d720becba..f3f730896 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -266,18 +266,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) miscRegName[misc_reg], val); } else { switch (misc_reg) { - case MISCREG_ITSTATE: - { - ITSTATE itstate = newVal; - CPSR cpsr = miscRegs[MISCREG_CPSR]; - cpsr.it1 = itstate.bottom2; - cpsr.it2 = itstate.top6; - miscRegs[MISCREG_CPSR] = cpsr; - DPRINTF(MiscRegs, - "Updating ITSTATE -> %#x in CPSR -> %#x.\n", - (uint8_t)itstate, (uint32_t)cpsr); - } - break; case MISCREG_CPACR: { CPACR newCpacr = 0; |