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| author | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:02 +0100 |
|---|---|---|
| committer | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:02 +0100 |
| commit | c53a57f74f31c2593665bae716c5c3679aab5595 (patch) | |
| tree | 292e4929f35d05d7fac170dacaccd720007269cf /src/arch/arm/isa.cc | |
| parent | 49538a71186d98f5440c5db646e23507fc2e38d1 (diff) | |
| download | gem5-c53a57f74f31c2593665bae716c5c3679aab5595.tar.xz | |
arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 2cf67fff7..2300b925e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1621,6 +1621,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_DACR: case MISCREG_VTTBR: case MISCREG_SCR_EL3: + case MISCREG_HCR_EL2: case MISCREG_TCR_EL1: case MISCREG_TCR_EL2: case MISCREG_TCR_EL3: |