diff options
author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
commit | c75ff71139d6358678835cca63e35d1135eaf466 (patch) | |
tree | 0811177db4dca4a237b8e5d7dd65f8ec155cb14e /src/arch/arm/isa.cc | |
parent | d99deff8ea296fd28b48da08aba577a1e7dfc01b (diff) | |
download | gem5-c75ff71139d6358678835cca63e35d1135eaf466.tar.xz |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 6f66e5ae1..d3286a6b0 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1521,8 +1521,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); Request req(0, val, 1, flags, Request::funcMasterId, - tc->pcState().pc(), tc->contextId(), - tc->threadId()); + tc->pcState().pc(), tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); HCR hcr = readMiscRegNoEffect(MISCREG_HCR); @@ -1768,7 +1767,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); req->setVirt(0, val, 1, flags, Request::funcMasterId, tc->pcState().pc()); - req->setThreadContext(tc->contextId(), tc->threadId()); + req->setContext(tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType); |