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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-25 18:23:17 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-08 15:28:12 +0000 |
| commit | 376f1b2ff7034f4d084a087a68307b11042d2a9d (patch) | |
| tree | 900b593a817104bc9345083f9952bbd3b8444bbf /src/arch/arm/isa.cc | |
| parent | 05ee4c5b53cd0eaee5725abf039285156dab2734 (diff) | |
| download | gem5-376f1b2ff7034f4d084a087a68307b11042d2a9d.tar.xz | |
arch-arm: Map ID_x_EL1 registers to AArch32 version
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those
registers must be initialized even when the highest Exception Level is
using AArch64.
Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 42d1b920b..296f8eb4a 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -118,6 +118,18 @@ ISA::clear() miscRegs[MISCREG_MIDR_EL1] = p->midr; miscRegs[MISCREG_VPIDR] = p->midr; + miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; + miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; + miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; + miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; + miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; + miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; + + miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; + miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; + miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; + miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; + if (FullSystem && system->highestELIs64()) { // Initialize AArch64 state clear64(p); @@ -208,18 +220,6 @@ ISA::clear() miscRegs[MISCREG_CPACR] = 0; - miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; - miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; - miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; - miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; - - miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; - miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; - miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; - miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; - miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; - miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; - miscRegs[MISCREG_FPSID] = p->fpsid; if (haveLPAE) { |