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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-08-02 10:38:01 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-08-02 10:38:01 +0100 |
| commit | 49538a71186d98f5440c5db646e23507fc2e38d1 (patch) | |
| tree | 96994897ff3faf3da05b44d2375afcc0b98140b9 /src/arch/arm/isa.cc | |
| parent | 4fbf40daab480ae02b75a75e0dd5f56ce38386d2 (diff) | |
| download | gem5-49538a71186d98f5440c5db646e23507fc2e38d1.tar.xz | |
arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index c90de1337..2cf67fff7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -359,9 +359,8 @@ ISA::clear64(const ArmISAParams *p) if (haveSecurity) { miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields - // @todo: uncomment this to enable Virtualization - // } else if (haveVirtualization) { - // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; + } else if (haveVirtualization) { + miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; } else { miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; // Always non-secure @@ -391,15 +390,13 @@ ISA::clear64(const ArmISAParams *p) // Enforce consistency with system-level settings... // EL3 - // (no AArch32/64 interprocessing support for now) miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, - haveSecurity ? 0x1 : 0x0); + haveSecurity ? 0x2 : 0x0); // EL2 - // (no AArch32/64 interprocessing support for now) miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, - haveVirtualization ? 0x1 : 0x0); + haveVirtualization ? 0x2 : 0x0); // Large ASID support miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, |