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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
| commit | 4a3f11149d791284a012af71067f6b2199aa165c (patch) | |
| tree | c960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/arch/arm/isa.cc | |
| parent | 035a82ee2c7e9ee72163a6559f721b242427906d (diff) | |
| download | gem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz | |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 38607a9ae..e76ff452d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013 ARM Limited + * Copyright (c) 2010-2014 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -599,9 +599,9 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_NZCV: { CPSR cpsr = 0; - cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ); - cpsr.c = tc->readIntReg(INTREG_CONDCODES_C); - cpsr.v = tc->readIntReg(INTREG_CONDCODES_V); + cpsr.nz = tc->readCCReg(CCREG_NZ); + cpsr.c = tc->readCCReg(CCREG_C); + cpsr.v = tc->readCCReg(CCREG_V); return cpsr; } case MISCREG_DAIF: @@ -1688,9 +1688,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) { CPSR cpsr = val; - tc->setIntReg(INTREG_CONDCODES_NZ, cpsr.nz); - tc->setIntReg(INTREG_CONDCODES_C, cpsr.c); - tc->setIntReg(INTREG_CONDCODES_V, cpsr.v); + tc->setCCReg(CCREG_NZ, cpsr.nz); + tc->setCCReg(CCREG_C, cpsr.c); + tc->setCCReg(CCREG_V, cpsr.v); } break; case MISCREG_DAIF: |