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| author | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:03 +0100 |
|---|---|---|
| committer | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:03 +0100 |
| commit | 4d5d47c173d3e649c7e620481d18ea93a3e09e79 (patch) | |
| tree | 2a3663fcc250d5c24b1992a6d7b84c2fdf94a1ed /src/arch/arm/isa.cc | |
| parent | 89511856fe15077d4f568e3226aff66d1f3b39eb (diff) | |
| download | gem5-4d5d47c173d3e649c7e620481d18ea93a3e09e79.tar.xz | |
arm: Add TLBI instruction for stage 2 IPA's
This patch adds support for stage 2 TLBI instructions
such as TLBI IPAS2E1_Xt.
Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 016e1eca0..fabbe0756 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1393,8 +1393,27 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_TLBI_IPAS2E1IS_Xt: case MISCREG_TLBI_IPAS2E1_Xt: assert64(tc); - // @todo: implement these as part of Virtualization - warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); + target_el = 1; // EL 0 and 1 are handled together + scr = readMiscReg(MISCREG_SCR, tc); + secure_lookup = haveSecurity && !scr.ns; + sys = tc->getSystemPtr(); + for (x = 0; x < sys->numContexts(); x++) { + oc = sys->getThreadContext(x); + assert(oc->getITBPtr() && oc->getDTBPtr()); + Addr ipa = ((Addr) bits(newVal, 35, 0)) << 12; + oc->getITBPtr()->flushIpaVmid(ipa, + secure_lookup, false, target_el); + oc->getDTBPtr()->flushIpaVmid(ipa, + secure_lookup, false, target_el); + + CheckerCPU *checker = oc->getCheckerCpuPtr(); + if (checker) { + checker->getITBPtr()->flushIpaVmid(ipa, + secure_lookup, false, target_el); + checker->getDTBPtr()->flushIpaVmid(ipa, + secure_lookup, false, target_el); + } + } return; case MISCREG_ACTLR: warn("Not doing anything for write of miscreg ACTLR\n"); |