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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-08-15 12:00:35 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-08-15 12:00:35 +0100 |
| commit | 698767e5384a664b3bad52c9b40d62daf0eabbfc (patch) | |
| tree | 2cb02cf387574c233367bfd6602b9ac271815384 /src/arch/arm/isa.cc | |
| parent | 608a37c844829715c2a15ef079f7dd8db428779b (diff) | |
| download | gem5-698767e5384a664b3bad52c9b40d62daf0eabbfc.tar.xz | |
cpu, arch: fix the type used for the request flags
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index fabbe0756..2ae0bd7dc 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1465,7 +1465,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_ATS1HR: case MISCREG_ATS1HW: { - unsigned flags = 0; + Request::Flags flags = 0; BaseTLB::Mode mode = BaseTLB::Read; TLB::ArmTranslationType tranType = TLB::NormalTran; Fault fault; @@ -1710,7 +1710,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_AT_S1E3W_Xt: { RequestPtr req = new Request; - unsigned flags = 0; + Request::Flags flags = 0; BaseTLB::Mode mode = BaseTLB::Read; TLB::ArmTranslationType tranType = TLB::NormalTran; Fault fault; |