O3: Make all instructions that write a misc. register not perform the write until commit.

ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR.  Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes.  Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).

1 files changed, 16 insertions, 1 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 87203c3f0..649394270 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -202,7 +202,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         warn("Not doing anyhting for read to miscreg %s\n",
                 miscRegName[misc_reg]);
         break;
-
+      case MISCREG_FPSCR_QC:
+        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
+      case MISCREG_FPSCR_EXC:
+        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
     }
     return readMiscRegNoEffect(misc_reg);
 }
@@ -304,6 +307,18 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
             }
             break;
+          case MISCREG_FPSCR_QC:
+            {
+                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);
+                misc_reg = MISCREG_FPSCR;
+            }
+            break;
+          case MISCREG_FPSCR_EXC:
+            {
+                newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask);
+                misc_reg = MISCREG_FPSCR;
+            }
+            break;
           case MISCREG_FPEXC:
             {
                 const uint32_t fpexcMask = 0x60000000;