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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2018-05-07 18:06:08 -0500 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-03 10:38:22 +0000 |
| commit | 8a9e0079e7fc89c7abbf7d360cd1707d11cd3df0 (patch) | |
| tree | c327a2d7211e1c3ddf26e531c55d65ad7c6d4d1d /src/arch/arm/isa.cc | |
| parent | ff7fc9de6955ba3e00898eb703b3da1a15fb417c (diff) | |
| download | gem5-8a9e0079e7fc89c7abbf7d360cd1707d11cd3df0.tar.xz | |
arm: properly handle RES0/1 for SCTLRs
They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.
Also fix this for HVBAR.
Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 319cc9c09..647ecf787 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -659,16 +659,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) return readMiscRegNoEffect(MISCREG_DFAR_S); case MISCREG_HIFAR: // alias for secure IFAR return readMiscRegNoEffect(MISCREG_IFAR_S); - case MISCREG_HVBAR: // bottom bits reserved - return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; - case MISCREG_SCTLR: - return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; - case MISCREG_SCTLR_EL1: - return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; - case MISCREG_SCTLR_EL2: - case MISCREG_SCTLR_EL3: - case MISCREG_HSCTLR: - return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; case MISCREG_ID_PFR0: // !ThumbEE | !Jazelle | Thumb | ARM |