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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
| commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
| tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/arch/arm/isa.cc | |
| parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
| download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz | |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 5c2478946..a609b3ef9 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -559,7 +559,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) panic("Security Extensions not implemented!"); } warn("Translating via MISCREG in atomic mode! Fix Me!\n"); - req->setVirt(0, val, 1, flags, tc->pcState().pc()); + req->setVirt(0, val, 1, flags, tc->pcState().pc(), + Request::funcMasterId); fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); if (fault == NoFault) { miscRegs[MISCREG_PAR] = |