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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-01 17:26:31 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-03-01 17:26:31 -0600 |
| commit | 91b737ed48008ed295db22c857183f040a63234c (patch) | |
| tree | 03e4be02cd6846b632045b520ad7d9a588974bc9 /src/arch/arm/isa.cc | |
| parent | 3876105bdb5589360c58389ffffff9786a93a2ff (diff) | |
| download | gem5-91b737ed48008ed295db22c857183f040a63234c.tar.xz | |
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b79b9346f..9d76ca60e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -213,8 +213,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) "config registers and jumping to ThumbEE vectors\n"); return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM case MISCREG_ID_PFR1: - warn("reading unimplmented register ID_PFR1"); - return 0; + return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 case MISCREG_CTR: return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact case MISCREG_ACTLR: |