diff options
author | Jairo Balart <jairo.balart@metempsy.com> | 2018-10-11 16:05:12 +0200 |
---|---|---|
committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-10 16:29:30 +0000 |
commit | 93c7fa573116aade8e8d6b0646e85874e6003567 (patch) | |
tree | 6e49e8be33c3514553017e055fc32a627cb68698 /src/arch/arm/isa.cc | |
parent | 7d5696d1a9f0776f51ec20e81a413fcdcc748c4e (diff) | |
download | gem5-93c7fa573116aade8e8d6b0646e85874e6003567.tar.xz |
dev-arm: Add a GICv3 model
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
-rw-r--r-- | src/arch/arm/isa.cc | 41 |
1 files changed, 37 insertions, 4 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 647ecf787..d7d51b887 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -48,6 +48,8 @@ #include "debug/Arm.hh" #include "debug/MiscRegs.hh" #include "dev/arm/generic_timer.hh" +#include "dev/arm/gic_v3.hh" +#include "dev/arm/gic_v3_cpu_interface.hh" #include "params/ArmISA.hh" #include "sim/faults.hh" #include "sim/stat_control.hh" @@ -94,6 +96,13 @@ ISA::ISA(Params *p) physAddrRange = 32; // dummy value } + // GICv3 CPU interface system registers are supported + haveGICv3CPUInterface = false; + + if (system && dynamic_cast<Gicv3 *>(system->getGIC())) { + haveGICv3CPUInterface = true; + } + initializeMiscRegMetadata(); preUnflattenMiscReg(); @@ -372,6 +381,13 @@ ISA::startup(ThreadContext *tc) { pmu->setThreadContext(tc); + if (system) { + Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); + if (gicv3) { + gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); + gicv3CpuInterface->setISA(this); + } + } } @@ -672,10 +688,11 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) | (haveTimer ? 0x00010000 : 0x0); } case MISCREG_ID_AA64PFR0_EL1: - return 0x0000000000000002 // AArch{64,32} supported at EL0 - | 0x0000000000000020 // EL1 - | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 - | (haveSecurity ? 0x0000000000002000 : 0); // EL3 + return 0x0000000000000002 | // AArch{64,32} supported at EL0 + 0x0000000000000020 | // EL1 + (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 + (haveSecurity ? 0x0000000000002000 : 0) | // EL3 + (haveGICv3CPUInterface ? 0x0000000001000000 : 0); case MISCREG_ID_AA64PFR1_EL1: return 0; // bits [63:0] RES0 (reserved for future use) @@ -689,6 +706,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: return getGenericTimer(tc).readMiscReg(misc_reg); + case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: + case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: + return getGICv3CPUInterface(tc).readMiscReg(misc_reg); + default: break; @@ -1965,6 +1986,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: getGenericTimer(tc).setMiscReg(misc_reg, newVal); break; + + case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: + case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: + getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); + return; } } setMiscRegNoEffect(misc_reg, newVal); @@ -1991,6 +2017,13 @@ ISA::getGenericTimer(ThreadContext *tc) return *timer.get(); } +BaseISADevice & +ISA::getGICv3CPUInterface(ThreadContext *tc) +{ + panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); + return *gicv3CpuInterface.get(); +} + } ArmISA::ISA * |