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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
| commit | 9cf6bc444b700bcf8140bb975e99cfdf13c3964c (patch) | |
| tree | 286f873448b08fa366638b308f380e90b4dc6713 /src/arch/arm/isa.cc | |
| parent | 7ddb55a5f2d0631d79cc8e871924adb189d7bae9 (diff) | |
| download | gem5-9cf6bc444b700bcf8140bb975e99cfdf13c3964c.tar.xz | |
arm: audit SCTLR
Change-Id: I814f1431a5f754f75721c9ac51171f860a714d24
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 25 |
1 files changed, 10 insertions, 15 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 1ba739374..034340049 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -211,9 +211,7 @@ ISA::ISA(Params *p) pmu(p->pmu), lookUpMiscReg(NUM_MISCREGS, {0,0}) { - SCTLR sctlr; - sctlr = 0; - miscRegs[MISCREG_SCTLR_RST] = sctlr; + miscRegs[MISCREG_SCTLR_RST] = 0; // Hook up a dummy device if we haven't been configured with a // real PMU. By using a dummy device, we don't need to check that @@ -432,12 +430,14 @@ ISA::clear64(const ArmISAParams *p) // Initialize other control registers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; if (haveSecurity) { - miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; + miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields } else if (haveVirtualization) { - miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; + // also MISCREG_SCTLR_EL2 (by mapping) + miscRegs[MISCREG_HSCTLR] = 0x30c50830; } else { - miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; + // also MISCREG_SCTLR_EL1 (by mapping) + miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init // Always non-secure miscRegs[MISCREG_SCR_EL3] = 1; } @@ -491,12 +491,9 @@ ISA::readMiscRegNoEffect(int misc_reg) const // registers are left unchanged MiscReg val; - if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR - || flat_idx == MISCREG_SCTLR_EL1) { + if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR) { if (flat_idx == MISCREG_SPSR) flat_idx = flattenMiscIndex(MISCREG_SPSR); - if (flat_idx == MISCREG_SCTLR_EL1) - flat_idx = flattenMiscIndex(MISCREG_SCTLR); val = miscRegs[flat_idx]; } else if (lookUpMiscReg[flat_idx].upper > 0) @@ -779,11 +776,11 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_SCTLR: return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; case MISCREG_SCTLR_EL1: - return (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; + return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; + case MISCREG_SCTLR_EL2: case MISCREG_SCTLR_EL3: - return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; case MISCREG_HSCTLR: - return readMiscRegNoEffect(MISCREG_HSCTLR); + return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: @@ -817,8 +814,6 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) } else { if (flat_idx == MISCREG_SPSR) flat_idx = flattenMiscIndex(MISCREG_SPSR); - else if (flat_idx == MISCREG_SCTLR_EL1) - flat_idx = flattenMiscIndex(MISCREG_SCTLR); else flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? lookUpMiscReg[flat_idx].lower : flat_idx; |