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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-23 11:19:50 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-12 10:23:50 +0000 |
| commit | a2df8b2f631b82b2830a64206fe50acbf12e7940 (patch) | |
| tree | 4c12f75ace5c920b1acde5c0529670602c38f97d /src/arch/arm/isa.cc | |
| parent | b3d0f2d66a5bf79f66893adcb85b0ac78daf3f65 (diff) | |
| download | gem5-a2df8b2f631b82b2830a64206fe50acbf12e7940.tar.xz | |
arch-arm: Implement missing aarch32 TLBI registers
In the pool of TLB Invalidate system register a category of instruction
was missing: the ones operating on entries added to the TLB during the
last level only of a table walk. (E.g. TLBIVMAL). This patch is not
considering this matching criteria when invalidating the entries and it
is rather performing the invalidation on all levels.
Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d6992dc44..4d27c9a22 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1062,8 +1062,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el); return; // TLBI based on VA, EL0&1 inner sharable (ignored) - case MISCREG_TLBIMVAIS: + case MISCREG_TLBIMVAL: + case MISCREG_TLBIMVALIS: + // mcr tlbimval(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. case MISCREG_TLBIMVA: + case MISCREG_TLBIMVAIS: assert32(tc); target_el = 1; // el 0 and 1 are handled together scr = readMiscReg(MISCREG_SCR, tc); @@ -1111,8 +1116,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } return; // TLBI by address, EL0&1, inner sharable (ignored) - case MISCREG_TLBIMVAAIS: + case MISCREG_TLBIMVAAL: + case MISCREG_TLBIMVAALIS: + // mcr tlbimvaal(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. case MISCREG_TLBIMVAA: + case MISCREG_TLBIMVAAIS: assert32(tc); target_el = 1; // el 0 and 1 are handled together scr = readMiscReg(MISCREG_SCR, tc); @@ -1121,6 +1131,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); return; // TLBI by address, EL2, hypervisor mode + case MISCREG_TLBIMVALH: + case MISCREG_TLBIMVALHIS: + // mcr tlbimvalh(is) is invalidating all matching entries + // regardless of the level of lookup, since in gem5 we cache + // in the tlb the last level of lookup only. case MISCREG_TLBIMVAH: case MISCREG_TLBIMVAHIS: assert32(tc); |