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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/arch/arm/isa.cc | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index bac7bab89..f90b8a2df 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -668,12 +668,12 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_DBGDSCRint: return 0; case MISCREG_ISR: - return tc->getCpuPtr()->getInterruptController()->getISR( + return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( readMiscRegNoEffect(MISCREG_HCR), readMiscRegNoEffect(MISCREG_CPSR), readMiscRegNoEffect(MISCREG_SCR)); case MISCREG_ISR_EL1: - return tc->getCpuPtr()->getInterruptController()->getISR( + return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( readMiscRegNoEffect(MISCREG_HCR_EL2), readMiscRegNoEffect(MISCREG_CPSR), readMiscRegNoEffect(MISCREG_SCR_EL3)); @@ -1929,7 +1929,7 @@ ISA::getGenericTimer(ThreadContext *tc) "been configured to use a generic timer.\n"); } - timer.reset(new GenericTimerISA(*generic_timer, tc->cpuId())); + timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); return *timer.get(); } |