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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:28 -0600 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:28 -0600 |
| commit | ae2e0ca3d08283ed3987e4217df843d5982847c5 (patch) | |
| tree | 55022a80c43694d64eb2722eb2f31bf0f7f4b634 /src/arch/arm/isa.cc | |
| parent | a73937b60c0057d006938bca7ec69a8b48450f2c (diff) | |
| download | gem5-ae2e0ca3d08283ed3987e4217df843d5982847c5.tar.xz | |
arm: compute ID_AA64PFR{0,1}_EL1 registers
Compute the proper values of the aforementioned registers from
the system configuration rather than configuring the values themselves.
Change-Id: If9774b6610a29568b80ae4866107b9a6a5b5be0f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 90325346c..74ea91a8d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -452,8 +452,6 @@ ISA::clear64(const ArmISAParams *p) miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; - miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; - miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; miscRegs[MISCREG_ID_DFR0_EL1] = (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 @@ -776,6 +774,13 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) return 0x00000001 | (haveSecurity ? 0x00000010 : 0x0) | (haveVirtualization ? 0x00001000 : 0x0); + case MISCREG_ID_AA64PFR0_EL1: + return 0x0000000000000002 // AArch{64,32} supported at EL0 + | 0x0000000000000020 // EL1 + | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 + | (haveSecurity ? 0x0000000000002000 : 0); // EL3 + case MISCREG_ID_AA64PFR1_EL1: + return 0; // bits [63:0] RES0 (reserved for future use) // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: |