Revert power patch sets with unexpected interactions

The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508

1 files changed, 3 insertions, 2 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d3286a6b0..6f66e5ae1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1521,7 +1521,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
               // with unexpected atomic snoop requests.
               warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
               Request req(0, val, 1, flags,  Request::funcMasterId,
-                          tc->pcState().pc(), tc->contextId());
+                          tc->pcState().pc(), tc->contextId(),
+                          tc->threadId());
               fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType);
               TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
               HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
@@ -1767,7 +1768,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
                 req->setVirt(0, val, 1, flags,  Request::funcMasterId,
                                tc->pcState().pc());
-                req->setContext(tc->contextId());
+                req->setThreadContext(tc->contextId(), tc->threadId());
                 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
                                                              tranType);