ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).

1 files changed, 17 insertions, 0 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 25bc3161b..676abfa68 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -360,6 +360,23 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
                 tc->getITBPtr()->invalidateMiscReg();
                 tc->getDTBPtr()->invalidateMiscReg();
+
+                // Check if all CPUs are booted with caches enabled
+                // so we can stop enforcing coherency of some kernel
+                // structures manually.
+                sys = tc->getSystemPtr();
+                for (x = 0; x < sys->numContexts(); x++) {
+                    oc = sys->getThreadContext(x);
+                    SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
+                    if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
+                        return;
+                }
+
+                for (x = 0; x < sys->numContexts(); x++) {
+                    oc = sys->getThreadContext(x);
+                    oc->getDTBPtr()->allCpusCaching();
+                    oc->getITBPtr()->allCpusCaching();
+                }
                 return;
             }
           case MISCREG_TLBTR: