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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-12-18 14:20:44 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-16 11:20:26 +0000 |
| commit | cba75858ab94b525c2daad973b8197e9ebd1f1af (patch) | |
| tree | e0cf1bcc94ce66e264afb127e9ad8f58a7a3467f /src/arch/arm/isa.cc | |
| parent | 671840615bb721b9545789555e796f5d47a15bf6 (diff) | |
| download | gem5-cba75858ab94b525c2daad973b8197e9ebd1f1af.tar.xz | |
arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled
Trying to read MPIDR(_EL1) from EL1, should return the value of
VMPIDR_EL2 if EL2 is enabled. This patch is modifying the utility
function for reading MPIDR in order to match this behaviour for both
AArch32 and AArch64.
Change-Id: I32c2d4d5052f509e6e0542a5314844164221c6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 17c87ba84..3d98aeacf 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -477,18 +477,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) return val; } case MISCREG_MPIDR: - cpsr = readMiscRegNoEffect(MISCREG_CPSR); - scr = readMiscRegNoEffect(MISCREG_SCR); - if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { - return getMPIDR(system, tc); - } else { - return readMiscReg(MISCREG_VMPIDR, tc); - } - break; case MISCREG_MPIDR_EL1: - // @todo in the absence of v8 virtualization support just return MPIDR_EL1 - return getMPIDR(system, tc) & 0xffffffff; + return readMPIDR(system, tc); case MISCREG_VMPIDR: + case MISCREG_VMPIDR_EL2: // top bit defined as RES1 return readMiscRegNoEffect(misc_reg) | 0x80000000; case MISCREG_ID_AFR0: // not implemented, so alias MIDR |