ARM: Remove the saturating (Q) condition code from the renamed register.

Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.

1 files changed, 9 insertions, 0 deletions

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 0db941462..27218bca8 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -216,6 +216,8 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         warn("Not doing anything for read to miscreg %s\n",
                 miscRegName[misc_reg]);
         break;
+      case MISCREG_CPSR_Q:
+        panic("shouldn't be reading this register seperately\n");
       case MISCREG_FPSCR_QC:
         return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
       case MISCREG_FPSCR_EXC:
@@ -316,6 +318,13 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
             }
             break;
+          case MISCREG_CPSR_Q:
+            {
+                assert(!(newVal & ~CpsrMaskQ));
+                newVal = miscRegs[MISCREG_CPSR] | newVal;
+                misc_reg = MISCREG_CPSR;
+            }
+            break;
           case MISCREG_FPSCR_QC:
             {
                 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask);