diff options
| author | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
|---|---|---|
| committer | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
| commit | e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1 (patch) | |
| tree | 2195fa893b9bcdcfe13db3e16d2f140b84e33d61 /src/arch/arm/isa.cc | |
| parent | d919930c3c7f5d364f211513742a51f56e36eaab (diff) | |
| download | gem5-e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1.tar.xz | |
ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 27218bca8..b8a047f65 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -186,12 +186,19 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_MPIDR: return tc->cpuId(); break; + case MISCREG_ID_MMFR0: + return 0x03; // VMSAv7 support + case MISCREG_ID_MMFR2: + return 0x01230000; // no HW access | WFI stalling | ISB and DSB + // | all TLB maintenance | no Harvard case MISCREG_ID_MMFR3: return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | // BP Maint | Cache Maint Set/way | Cache Maint MVA case MISCREG_CLIDR: warn_once("The clidr register always reports 0 caches.\n"); - break; + warn_once("clidr LoUIS field of 0b001 to match current " + "ARM implementations.\n"); + return 0x00200000; case MISCREG_CCSIDR: warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); @@ -203,8 +210,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_ID_PFR1: warn("reading unimplmented register ID_PFR1"); return 0; - case MISCREG_ID_MMFR0: - return 0x03; //VMSAz7 case MISCREG_CTR: return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact case MISCREG_ACTLR: |