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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-17 17:19:53 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-07-16 08:18:56 +0000 |
| commit | e7f6e7cd26de7d37c63d6642c576c1b97758340a (patch) | |
| tree | b882bb7ef4d7bbf6348e184980f279d7d38e8de5 /src/arch/arm/isa.cc | |
| parent | cb09573e52d05d71587a93fbde310147492eacef (diff) | |
| download | gem5-e7f6e7cd26de7d37c63d6642c576c1b97758340a.tar.xz | |
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers
into the decode tree. They are currently implemented as a generic timer
and produces a warning if accessed.
Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11592
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9b17927e0..c701cc3a7 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -644,6 +644,9 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) return 0; // bits [63:0] RES0 (reserved for future use) // Generic Timer registers + case MISCREG_CNTHV_CTL_EL2: + case MISCREG_CNTHV_CVAL_EL2: + case MISCREG_CNTHV_TVAL_EL2: case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: @@ -1913,6 +1916,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) break; // Generic Timer registers + case MISCREG_CNTHV_CTL_EL2: + case MISCREG_CNTHV_CVAL_EL2: + case MISCREG_CNTHV_TVAL_EL2: case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: |