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| author | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2017-02-09 18:54:28 -0500 |
|---|---|---|
| committer | Bjoern A. Zeeb <baz21@cam.ac.uk> | 2017-02-09 18:54:28 -0500 |
| commit | f0786704db90b0020066d19652886b9311516b45 (patch) | |
| tree | 56bcb4ec6451d4df047abb9b8ac91ee69638aa0a /src/arch/arm/isa.cc | |
| parent | 653b4657e67f24339abd18a154a57ca5d578b4b9 (diff) | |
| download | gem5-f0786704db90b0020066d19652886b9311516b45.tar.xz | |
arm: AArch64 report cache size correctly when reading CTR_EL0
Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not
implmemented. With that an operating system relying on the cache line
sizes reported in order to manage the caches would (a) panic given the
returned value 0 is not valid (high bit is RES1) or (b) worst case would
assume a cache line size of 4 doing a tremendous amount of extra
instruction work (including fetching). Return the same values as for ARMv7
as the fields seem to be the same, or RES0/1 seem to be reported
accordingly for AArch64
In collaboration with: Andrew Turner
Testing Done: Checked on FreeBSD boots with extra printfs; also observed a
reduction of a factor of about 10 in instruction fetches for a simple
micro-test.
Reviewed at http://reviews.gem5.org/r/3667/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0db6d433d..c54d7746d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -594,7 +594,8 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); break; - case MISCREG_CTR: + case MISCREG_CTR: // AArch32, ARMv7, top bit set + case MISCREG_CTR_EL0: // AArch64 { //all caches have the same line size in gem5 //4 byte words in ARM |