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| author | Jairo Balart <jairo.balart@metempsy.com> | 2018-10-11 16:05:12 +0200 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-10 16:29:30 +0000 |
| commit | 93c7fa573116aade8e8d6b0646e85874e6003567 (patch) | |
| tree | 6e49e8be33c3514553017e055fc32a627cb68698 /src/arch/arm/isa.hh | |
| parent | 7d5696d1a9f0776f51ec20e81a413fcdcc748c4e (diff) | |
| download | gem5-93c7fa573116aade8e8d6b0646e85874e6003567.tar.xz | |
dev-arm: Add a GICv3 model
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 65d2251f8..1ec0f4676 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -82,6 +82,9 @@ namespace ArmISA // Generic timer interface belonging to this ISA std::unique_ptr<BaseISADevice> timer; + // GICv3 CPU interface belonging to this ISA + std::unique_ptr<BaseISADevice> gicv3CpuInterface; + // Cached copies of system-level properties bool highestELIs64; bool haveSecurity; @@ -89,6 +92,7 @@ namespace ArmISA bool haveVirtualization; bool haveCrypto; bool haveLargeAsid64; + bool haveGICv3CPUInterface; uint8_t physAddrRange; /** @@ -400,6 +404,7 @@ namespace ArmISA } BaseISADevice &getGenericTimer(ThreadContext *tc); + BaseISADevice &getGICv3CPUInterface(ThreadContext *tc); private: |