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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:57:59 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:57:59 -0500
commit9ef82c0bc437a962398857dcb365a8493a9ac5c7 (patch)
tree72a8bb547981a08249aac1f3af9d36641220d9c3 /src/arch/arm/isa.hh
parent1c0d9806e5475e07fd62e56938bde77f52496cfb (diff)
downloadgem5-9ef82c0bc437a962398857dcb365a8493a9ac5c7.tar.xz
ARM: Track the current ISA mode using the PC.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r--src/arch/arm/isa.hh33
1 files changed, 33 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 905eb0183..c64f7bef9 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
@@ -127,6 +139,19 @@ namespace ArmISA
MiscReg
readMiscReg(int misc_reg, ThreadContext *tc)
{
+ if (misc_reg == MISCREG_CPSR) {
+ CPSR cpsr = miscRegs[misc_reg];
+ Addr pc = tc->readPC();
+ if (pc & (ULL(1) << PcJBitShift))
+ cpsr.j = 1;
+ else
+ cpsr.j = 0;
+ if (pc & (ULL(1) << PcTBitShift))
+ cpsr.t = 1;
+ else
+ cpsr.t = 0;
+ return cpsr;
+ }
return readMiscRegNoEffect(misc_reg);
}
@@ -171,6 +196,14 @@ namespace ArmISA
{
if (misc_reg == MISCREG_CPSR) {
updateRegMap(val);
+ CPSR cpsr = val;
+ Addr npc = tc->readNextPC() & ~PcModeMask;
+ if (cpsr.j)
+ npc = npc | (ULL(1) << PcJBitShift);
+ if (cpsr.t)
+ npc = npc | (ULL(1) << PcTBitShift);
+
+ tc->setNextPC(npc);
}
return setMiscRegNoEffect(misc_reg, val);
}