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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:13 -0500 |
commit | eac239b4d6f6d9eccb3837330e3f22acefc1b48e (patch) | |
tree | 7d320f4db0aeab18124240fd11ca183dbcaab53e /src/arch/arm/isa.hh | |
parent | 9fb573d91e96f06505311462d902300b72b4b9a0 (diff) | |
download | gem5-eac239b4d6f6d9eccb3837330e3f22acefc1b48e.tar.xz |
ARM: Handle accesses to TLBTR.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index f4ff58a28..41382e510 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -131,6 +131,9 @@ namespace ArmISA (0 << 0) | //Revision 0; + // Separate Instruction and Data TLBs. + miscRegs[MISCREG_TLBTR] = 1; + //XXX We need to initialize the rest of the state. } @@ -269,6 +272,8 @@ namespace ArmISA case MISCREG_CSSELR: warn("The csselr register isn't implemented.\n"); break; + case MISCREG_TLBTR: + return; } return setMiscRegNoEffect(misc_reg, newVal); } |