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| author | Korey Sewell <ksewell@umich.edu> | 2009-07-31 10:40:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-07-31 10:40:42 -0400 |
| commit | aa75b9a7a7489bf86c4e6d406ff612e596ddff96 (patch) | |
| tree | 58a6816583a21c19c181e32bff10bf74aa9ad15f /src/arch/arm/isa.hh | |
| parent | 60063cc700912666fa8b7968d692d00a1e82cb67 (diff) | |
| parent | 3dd3de5feb31055a48acb39575da25a9cea2626d (diff) | |
| download | gem5-aa75b9a7a7489bf86c4e6d406ff612e596ddff96.tar.xz | |
merge mips fix and statetrace changes
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 39acc9c08..2315afa9e 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -48,7 +48,11 @@ namespace ArmISA public: void clear() { - // Unknown startup state currently + memset(miscRegs, 0, sizeof(miscRegs)); + CPSR cpsr = 0; + cpsr.mode = MODE_USER; + miscRegs[MISCREG_CPSR] = cpsr; + //XXX We need to initialize the rest of the state. } MiscReg |