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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
| commit | 282cf5807d827d5583e5cd5bffae75c4e5efb116 (patch) | |
| tree | 5a6893f52b49478b3c2fb6214d0eedb73b249b7e /src/arch/arm/isa.hh | |
| parent | 9cf6bc444b700bcf8140bb975e99cfdf13c3964c (diff) | |
| download | gem5-282cf5807d827d5583e5cd5bffae75c4e5efb116.tar.xz | |
arm: miscreg refactoring
Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 79db09e1d..e05f0e18a 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -79,6 +79,7 @@ namespace ArmISA std::unique_ptr<BaseISADevice> timer; // Cached copies of system-level properties + bool highestELIs64; bool haveSecurity; bool haveLPAE; bool haveVirtualization; @@ -328,7 +329,7 @@ namespace ArmISA } } else { if (miscRegInfo[reg][MISCREG_BANKED]) { - bool secureReg = haveSecurity && + bool secureReg = haveSecurity && !highestELIs64 && inSecureState(miscRegs[MISCREG_SCR], miscRegs[MISCREG_CPSR]); flat_idx += secureReg ? 2 : 1; @@ -337,11 +338,33 @@ namespace ArmISA return flat_idx; } + std::pair<int,int> getMiscIndices(int misc_reg) const + { + // Note: indexes of AArch64 registers are left unchanged + int flat_idx = flattenMiscIndex(misc_reg); + + if (lookUpMiscReg[flat_idx].lower == 0) { + return std::make_pair(flat_idx, 0); + } + + // do additional S/NS flattenings if mapped to NS while in S + bool S = haveSecurity && !highestELIs64 && + inSecureState(miscRegs[MISCREG_SCR], + miscRegs[MISCREG_CPSR]); + int lower = lookUpMiscReg[flat_idx].lower; + int upper = lookUpMiscReg[flat_idx].upper; + // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op) + lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD]; + upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD]; + return std::make_pair(lower, upper); + } + void serialize(CheckpointOut &cp) const { DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); SERIALIZE_ARRAY(miscRegs, NumMiscRegs); + SERIALIZE_SCALAR(highestELIs64); SERIALIZE_SCALAR(haveSecurity); SERIALIZE_SCALAR(haveLPAE); SERIALIZE_SCALAR(haveVirtualization); @@ -355,6 +378,7 @@ namespace ArmISA CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); + UNSERIALIZE_SCALAR(highestELIs64); UNSERIALIZE_SCALAR(haveSecurity); UNSERIALIZE_SCALAR(haveLPAE); UNSERIALIZE_SCALAR(haveVirtualization); |