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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
| commit | 43980752546cfa7ca90a11f0a2b68e1657dc6cab (patch) | |
| tree | 8c5caed292124aaae7d50e63743cfb8c54c1d9d3 /src/arch/arm/isa.hh | |
| parent | 2d08b8de9166552a3214012ecdfb98bd8fd3eafb (diff) | |
| download | gem5-43980752546cfa7ca90a11f0a2b68e1657dc6cab.tar.xz | |
ARM: Make various bits of the FP control registers read only.
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 1dad82397..f2d913ac4 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -295,10 +295,43 @@ namespace ArmISA case MISCREG_CSSELR: warn("The csselr register isn't implemented.\n"); break; + case MISCREG_FPSCR: + { + const uint32_t ones = (uint32_t)(-1); + FPSCR fpscrMask = 0; + fpscrMask.ioc = ones; + fpscrMask.dzc = ones; + fpscrMask.ofc = ones; + fpscrMask.ufc = ones; + fpscrMask.ixc = ones; + fpscrMask.idc = ones; + fpscrMask.len = ones; + fpscrMask.stride = ones; + fpscrMask.rMode = ones; + fpscrMask.fz = ones; + fpscrMask.dn = ones; + fpscrMask.ahp = ones; + fpscrMask.qc = ones; + fpscrMask.v = ones; + fpscrMask.c = ones; + fpscrMask.z = ones; + fpscrMask.n = ones; + newVal = (newVal & (uint32_t)fpscrMask) | + (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); + } + break; + case MISCREG_FPEXC: + { + const uint32_t fpexcMask = 0x60000000; + newVal = (newVal & fpexcMask) | + (miscRegs[MISCREG_FPEXC] & ~fpexcMask); + } + break; case MISCREG_TLBTR: case MISCREG_MVFR0: case MISCREG_MVFR1: case MISCREG_MPIDR: + case MISCREG_FPSID: return; } return setMiscRegNoEffect(misc_reg, newVal); |