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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-05-23 13:46:52 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-05-23 13:46:52 +0100 |
| commit | 65f3f097d3c270d2f28fc7d55651afaefb56ceed (patch) | |
| tree | 099c9667e246b9e8197f292c1880d9f7a3af9159 /src/arch/arm/isa.hh | |
| parent | 5435f25ec80ff691c4e42e06888c60a01848a31d (diff) | |
| download | gem5-65f3f097d3c270d2f28fc7d55651afaefb56ceed.tar.xz | |
dev, arm: Refactor and clean up the generic timer model
This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index fd9801ae2..11f25de6d 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2014 ARM Limited + * Copyright (c) 2010, 2012-2015 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -49,7 +49,6 @@ #include "arch/arm/tlb.hh" #include "arch/arm/types.hh" #include "debug/Checkpoint.hh" -#include "dev/arm/generic_timer.hh" #include "sim/sim_object.hh" struct ArmISAParams; @@ -139,6 +138,9 @@ namespace ArmISA // PMU belonging to this ISA BaseISADevice *pmu; + // Generic timer interface belonging to this ISA + std::unique_ptr<BaseISADevice> timer; + // Cached copies of system-level properties bool haveSecurity; bool haveLPAE; @@ -205,9 +207,7 @@ namespace ArmISA } } - ::GenericTimer::SystemCounter * getSystemCounter(ThreadContext *tc); - ::GenericTimer::ArchTimer * getArchTimer(ThreadContext *tc, - int cpu_id); + BaseISADevice &getGenericTimer(ThreadContext *tc); private: |