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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-22 14:14:48 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-03-23 10:24:24 +0000
commit9c8af4292004d0f2337dcc7eb45a56993e3719c9 (patch)
tree96a34214f4cb5d60db050d7b1ef1998fa3a65084 /src/arch/arm/isa.hh
parent33bb1aa386fd6e6b4bc93797e129bc5c4baa6a36 (diff)
downloadgem5-9c8af4292004d0f2337dcc7eb45a56993e3719c9.tar.xz
arch-arm: Distinguish IS TLBI from non-IS
TLBI broadcasting was the default implementation of most of TLBI instructions. This patch applies the broadcasting behaviour only to the Inner-Shareable subset, while simpler TLB invalidation instructions only affect the PE that executes them. Change-Id: Idb01d0d4f593131f657e8fc9668112de8e4ccdcb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9182 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r--src/arch/arm/isa.hh16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 05d118c4d..c10a88a37 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -391,22 +391,6 @@ namespace ArmISA
assert(!cpsr.width);
}
- void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
- bool secure_lookup, uint8_t target_el);
-
- void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);
-
- void tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el);
-
- void tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
- bool hyp, uint8_t target_el);
-
- void tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup,
- uint8_t target_el);
-
- void tlbiASID(ThreadContext *tc, uint16_t asid, bool secure_lookup,
- uint8_t target_el);
-
public:
void clear();
void clear64(const ArmISAParams *p);