cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705

1 files changed, 40 insertions, 0 deletions

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8de90dc93..e96de7922 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -48,7 +48,9 @@
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
 #include "arch/arm/types.hh"
+#include "arch/generic/traits.hh"
 #include "debug/Checkpoint.hh"
+#include "enums/VecRegRenameMode.hh"
 #include "sim/sim_object.hh"
 #include "enums/DecoderFlavour.hh"
 
@@ -68,6 +70,7 @@ namespace ArmISA
 
         // Micro Architecture
         const Enums::DecoderFlavour _decoderFlavour;
+        const Enums::VecRegRenameMode _vecRegRenameMode;
 
         /** Dummy device for to handle non-existing ISA devices */
         DummyISADevice dummyDevice;
@@ -185,6 +188,10 @@ namespace ArmISA
                 return RegId(IntRegClass, flattenIntIndex(regId.index()));
               case FloatRegClass:
                 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+              case VecRegClass:
+                return RegId(VecRegClass, flattenVecIndex(regId.index()));
+              case VecElemClass:
+                return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
               case CCRegClass:
                 return RegId(CCRegClass, flattenCCIndex(regId.index()));
               case MiscRegClass:
@@ -233,6 +240,20 @@ namespace ArmISA
         }
 
         int
+        flattenVecIndex(int reg) const
+        {
+            assert(reg >= 0);
+            return reg;
+        }
+
+        int
+        flattenVecElemIndex(int reg) const
+        {
+            assert(reg >= 0);
+            return reg;
+        }
+
+        int
         flattenCCIndex(int reg) const
         {
             assert(reg >= 0);
@@ -406,6 +427,12 @@ namespace ArmISA
 
         Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
 
+        Enums::VecRegRenameMode
+        vecRegRenameMode() const
+        {
+            return _vecRegRenameMode;
+        }
+
         /// Explicitly import the otherwise hidden startup
         using SimObject::startup;
 
@@ -417,4 +444,17 @@ namespace ArmISA
     };
 }
 
+template<>
+struct initRenameMode<ArmISA::ISA>
+{
+    static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa)
+    {
+        return isa->vecRegRenameMode();
+    }
+    static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)
+    {
+        return mode(isa1) == mode(isa2);
+    }
+};
+
 #endif