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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-10 20:34:38 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-10 20:34:38 -0800 |
| commit | 2e28da5583814efe1e0a09718f6a674f983d12d1 (patch) | |
| tree | 28f95117047652c1dceec3eef6f239f6d278ece4 /src/arch/arm/isa.hh | |
| parent | 4779020e139c70355335729b504195a0e5009e7a (diff) | |
| download | gem5-2e28da5583814efe1e0a09718f6a674f983d12d1.tar.xz | |
ARM: Implement fault classes.
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index a4a328614..a270f046b 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -85,6 +85,14 @@ namespace ArmISA cpsr.mode = MODE_USER; miscRegs[MISCREG_CPSR] = cpsr; updateRegMap(cpsr); + + SCTLR sctlr = 0; + sctlr.nmfi = 1; + sctlr.rao1 = 1; + sctlr.rao2 = 1; + sctlr.rao3 = 1; + sctlr.rao4 = 1; + //XXX We need to initialize the rest of the state. } |