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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
| commit | 4a3f11149d791284a012af71067f6b2199aa165c (patch) | |
| tree | c960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/arch/arm/isa.hh | |
| parent | 035a82ee2c7e9ee72163a6559f721b242427906d (diff) | |
| download | gem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz | |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index c72d5d50f..8341cd76b 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013 ARM Limited + * Copyright (c) 2010, 2012-2014 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -268,19 +268,21 @@ namespace ArmISA int flattenFloatIndex(int reg) const { + assert(reg >= 0); return reg; } - // dummy int flattenCCIndex(int reg) const { + assert(reg >= 0); return reg; } int flattenMiscIndex(int reg) const { + assert(reg >= 0); int flat_idx = reg; if (reg == MISCREG_SPSR) { |