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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-24 15:53:43 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-16 09:32:53 +0000 |
| commit | 8e17f07c295cec854d89cbf427bbd2f8dd915eda (patch) | |
| tree | 474b9791cdbb5920fa3b3ceff107b82d9a62184c /src/arch/arm/isa.hh | |
| parent | 94553f32d8dbb7979dbeb0e6bafaa5db1985db1e (diff) | |
| download | gem5-8e17f07c295cec854d89cbf427bbd2f8dd915eda.tar.xz | |
arch-arm: Arch regs and pseudo regs distinction
A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used
as a boundary for the number of physical (real) Misc registers in the
system. Pseudo registers (like CP15_UNIMPL) have been moved after the
NUM_PHYS_MISCREGS identifier, so that their enum number is
(NUM_PHYS_MISCREGS < number < NUM_MISCREGS). Moving away those
registers has created some free slots that can be used for future Misc
register implementation.
SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers.
This allows us to define as many pseudo registers as we want without
being concerned about checkpoint compatibility.
Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7921
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 1711ee0be..aa905e500 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2017 ARM Limited + * Copyright (c) 2010, 2012-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -629,7 +629,7 @@ namespace ArmISA void serialize(CheckpointOut &cp) const { DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); - SERIALIZE_ARRAY(miscRegs, NumMiscRegs); + SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); SERIALIZE_SCALAR(highestELIs64); SERIALIZE_SCALAR(haveSecurity); @@ -641,7 +641,7 @@ namespace ArmISA void unserialize(CheckpointIn &cp) { DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); - UNSERIALIZE_ARRAY(miscRegs, NumMiscRegs); + UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); |