arm: Fix multi-system AArch64 boot w/caches.

Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.

1 files changed, 8 insertions, 0 deletions

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 9f7fa111e..ae5ff2131 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -429,6 +429,14 @@ namespace ArmISA
 
         void startup(ThreadContext *tc) {}
 
+        /** Check if all CPUs have their caches enabled and if they do
+         * disable the bootAddrUncacheability flag because it's no longer
+         * needed.
+         * @s_idx the register number of the SCTLR that we are checking
+         * @tc Threadcontext to use to get access to the system and other cpus
+         */
+        void updateBootUncacheable(int sctlr_idx, ThreadContext *tc);
+
         /// Explicitly import the otherwise hidden startup
         using SimObject::startup;