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| author | Mitch Hayenga <mitch.hayenga+gem5@gmail.com> | 2013-01-08 08:54:07 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga+gem5@gmail.com> | 2013-01-08 08:54:07 -0500 |
| commit | c7dbd5e7686bbb065dfe2a74b92f4d9463ddfa80 (patch) | |
| tree | c7032e991c9e5d15e1d06f4695be9538e33ba3de /src/arch/arm/isa.hh | |
| parent | dc4a0aa2fa1bc3767785b552159ab0ebe5baa72e (diff) | |
| download | gem5-c7dbd5e7686bbb065dfe2a74b92f4d9463ddfa80.tar.xz | |
mem: Make LL/SC locks fine grained
The current implementation in gem5 just keeps a list of locks per cacheline.
Due to this, a store to a non-overlapping portion of the cacheline can cause an
LL/SC pair to fail. This patch simply adds an address range to the lock
structure, so that the lock is only invalidated if the store overlaps the lock
range.
Diffstat (limited to 'src/arch/arm/isa.hh')
0 files changed, 0 insertions, 0 deletions