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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-09 17:52:37 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-29 10:17:47 +0000 |
| commit | f94f70237dfaac86c83dfbb7cb24e6a821b867eb (patch) | |
| tree | 31fd902bb76d6024e1eac46d301de40fb9db6ec9 /src/arch/arm/isa.hh | |
| parent | 936b584ce35c079db98ab17c6ac9c6943ce7220e (diff) | |
| download | gem5-f94f70237dfaac86c83dfbb7cb24e6a821b867eb.tar.xz | |
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.
Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index c8ae5c22d..9158b62aa 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -90,6 +90,12 @@ namespace ArmISA bool haveLargeAsid64; uint8_t physAddrRange64; + /** + * If true, accesses to IMPLEMENTATION DEFINED registers are treated + * as NOP hence not causing UNDEFINED INSTRUCTION. + */ + bool impdefAsNop; + /** MiscReg metadata **/ struct MiscRegLUTEntry { uint32_t lower; // Lower half mapped to this register |